Work Package 4 – Electronics and readout

Calorimeter electronics exhibit several commonalities, such as large dynamic range (10-16 bits), very low noise, high accuracy (< 1%) and usually large capacitance (100’s of pF). This also makes them specific compared with other detectors. The recent trend has been a sharp increase in granularity (“imaging calorimeters”) and sub-ns timing capability (“5D calorimetry”) to allow for better particle reconstruction. This has led to the development of low-power highly integrated embedded electronics, integrated inside ASICs.
R&D developments will focus on reducing the power dissipation by at least an order of magnitude, down to ∼1 mW/ch in order to further increase the granularity in Work Package 1 or allow cryogenic operation without creating deadly bubbles in Work Package 2. For Work Package 3, improving the timing performance will also be an important asset. It will be pursued by exploiting the lower occupancy of future experiments at e+e−colliders, compared with HL-LHC, allowing slower shaping and on-chip data processing in order to reduce the output bandwidth. Various front-end electronics will be studied to optimise the dynamic range handling (dynamic gain switching, multi-gain preamps, ToT technique…). ADC/TDCs, digital logic will also be studied in order to reduce their power dissipation and in particular their instantaneous current spikes and minimise digital noise, which is a recurrent issue in calorimetry mixed-signal ASICs.

Coordinator: Christophe de la Taille (taille@in2p3.fr)